EDN

4-bit Counter

Designed a 4-bit counter using a J-K flip-flop that has a clocked input with reset. Performed simulations of various output parameters like rise time and fall time. The design is done using cadence ...
Design-Reuse

High Density - Low power Flip-Flop

Gaurav Goyal, Reecha Jajodia, Shahab Akhtar; Freescale Semiconductor India Pvt. Ltd. In a current trend of SoC Design, IC’s are becoming more and more complex so the challenges of meeting all the ...
Embedded

Using multi-bit flip-flop custom cells to achieve better SoC design efficiency

System-on-chip (SoC) designs are becoming more and more complex, by whatever means you measure it: power domains, gate count, packing densities, heat dissipation capacities, etc. At such high packing ...
EDN

Frequency Divider Using T Flip Flop Configuration

The circuit was constructed to produce a frequency divider with the use of flip flops which are the basic building blocks of sequential logic circuits while forming a T flip-flop configuration. Toggle ...
Design-Reuse

Usage of Multibit Flip-Flop and its Challenges in ASIC Physical Design

The continuous need for reduced size of the chip in the VLSI industry brings exciting challenges to the layout engineers for designing better and high-performing integrated circuits, which needs to ...
Electronics Weekly

e-Book on flip-flops

element14 has published an a eBook on how flip-flops work and their potential applications. The eBook provides a brief overview of the concept and offers insights into the functionality and different ...