Design-Reuse

A Low Complexity Parallel Architecture of Turbo Decoder Based on QPP Interleaver for 3GPP-LTE/LTE-A

This paper propose an improved method called the modified warm-up-free parallel window(PW) MAP decoding schemes to implement highly-parallel Turbo decoder architecture based on the QPP(Quadratic ...
Design-Reuse

Xilinx Meets Performance Requirements of LTE Wireless Systems With New LogiCORE Turbo Encoder and Decoder Solutions

BEIJING -- May 30, 2008-- Xilinx Inc. (Nasdaq: XLNX), the world's leading supplier of programmable logic solutions, today announced immediate availability of performance-optimized programmable turbo ...
EDN

Lattice expands wireless solutions with 3FPP-LTE CTC decoder IP core

The folks at Lattice have announced the availability of a 3GPP-Long-Term Evolution (LTE) Convolutional Turbo Code (CTC) Decoder intellectual property (IP) core from TurboConcept, a member of the ...
Electronic Design

LTE Comm Processor Implements Mutli Dispatch VLIW Architecture

Tensilica has delivered a range of processor architectures like the Xtensa LX (see Power Play For The SoC Developers) as well as DSP and the ConnX comm processor (see Dataplane Processing Unit More ...
EDN

Xilinx Meets Performance Requirements of LTE Wireless Systems With New LogiCORE Turbo Encoder and Decoder Solu

Xilinx Meets Performance Requirements of LTE Wireless Systems With New LogiCORE Turbo Encoder and Decoder SolutionsDelivers 5X throughput boost to developers of next-generation wireless systems ...