As the minimum feature size of semiconductor processes shrink, tooling costs escalate. Moreover, smaller minimum feature size leads to higher gate counts. Consequently, full-custom designs using ...

The high-speed ECC Accelerator reaches to more than a thousand operations per second in a modern FPGA or ASIC. Furthermore, it covers all NIST P curves with a single IP core instance and also allows ...

The IoT PLL is designed for very low power, sipping only 45uW at 30MHz and running from core power. It has a wide frequency range with multiplication factors up to 8192, allowing the PLL to run off of ...

Today there are various efficient, reusable and reliable functional verification methodologies available for Digital Design/SoC’s. Verification done using these methodologies ensures 99.99% functional ...

The newest member of the MIPI® PHY family, the C-PHY SM, arrived in October 2014 to a mixture of excitement and apprehension. How would this new C-PHY compare to the MIPI D-PHY SM and M-PHY®? What ...

NeoFuse is a logic-process compatible non-volatile memory (logic-NVM) using impedance change for data storage in one-time programming (OTP) applications. Storing data through NeoFuse can enable ...

The main objective of this paper is to explain the various types of design rule checks (DRC) violation, their causes and how to fix the various design rule checks (DRC) at lower technology node on ...

This paper describes the use of behavioral models and mixed-signal simulation as a means to verify the proper instantiation, connectivity and control of analog and mixed-signal (AMS) intellectual ...

With increasing complexities in power architecture and complex power domain partitioning, it is becoming imperative to drive functional and physical verification of these complex power logic hand in ...

Abstract— Today’s on-chip Analog/Mixed-Signal and RF (A/RF) systems have reached a limit of size and complexity where transistor-level SPICE and FastSPICE simulation approaches cannot deliver a ...

Suchang Chae, ETRI Daejeon Korea Abstract : This paper propose an improved method called the modified warm-up-free parallel window(PW) MAP decoding schemes to implement highly-parallel Turbo decoder ...

The OTG PHY supports up to UTMI+ level 3. The area and power is pretty minimal compared with other vendors. In order to minimize the power and area, innovative architecture and techniques are used in ...